Progress made in technology for reducing the size of semiconductor devices introduces new constraints. For devices made using MOS technology, such as MOSFETS (Metal-Oxide Semiconductor Field-Effect Transistors), the reduction in the gate widths causes a reduction in the threshold voltage. It is sometimes necessary to have a high threshold voltage, for example in MOS transistors used in an SRAM or DRAM. This is usually done by increasing the channel doping levels in order to increase threshold voltages of these transistors. But one consequence is, for example, to increase leakage currents at drain-substrate and source-substrate junctions (referred to herein as drain (source)—substrate junctions). This increase in leakage currents may be critical for these devices, particularly for memories such as an SRAM and DRAM.
It is also known that supplementary implants of doping agents can be made in the substrate to increase the threshold voltages of these transistors, in addition to channel doping done during manufacture of a MOS type transistor, for example. One known method for implantation of doping agents in a device 1 made using MOS technology is shown in FIG. 1.
In FIG. 1, the device 1 is an NMOS transistor 13. The device 1 includes a substrate 8 and a gate 2 arranged on a face 12 of the substrate S. The N+ doped regions 3 and 4 arranged on each side of a channel 15 of the NMOS transistor 13 form doped source and drain regions of the NMOS transistor 13. Before the gate 2 is made, the substrate 8 is subjected to a vertical ionic implantation of phosphorus, forming a first N doped region 9 throughout the substrate 8. Production of this first region 9 is a first step in the doping agent implantation method.
After the gate 2 has been formed on the substrate 8, a second ionic implantation of N doping agents is made at the first region 9, forming a second N doped region 10 called a pocket. This is done by making the ionic implantation using ion beams 11 inclined at an angle of about 25° from normal to the plane defined by the face 12 of the substrate B.
The pocket 10 thus created is distributed in the channel 15, but also in the drain region 4 at a depth of about 10 to 15 nanometers below the surface 12, for example. This operation may be repeated four times by rotating by 90° each time normal to the plane defined by the face 12 of the substrate 8. Each time a new pocket 10 is created in the channel 15 and the source region 3 and the drain region 4. In FIG. 1, only one pocket 10 is shown corresponding to the first ionic implantation. The device 1 is then annealed, causing the diffusion of doping agents located in the pockets 10 throughout the channel 15 of the NMOS transistor 13 of the device 1.
But the device 1 for which the channel 15 includes doping agents implanted using this method has high leakage currents, for example, about 30 to 40 pA. This is particularly at the drain (source)—substrate junction, and is due to the distribution of doping agents throughout the channel 15, and also in the source and drain regions 3, 4.